When the output is charging, the time constant is now dependent upon the resistance of the transistor T4, diode D1 and R4. To reduce this we could just reduce the value of R3 but then the power consumption will increase when the output transistor T1 is on. ‘0’ to ‘1’）is limited by the time constant R3 x CL. Hence the delay time for the output to charge from low to high (i.e. 9.2(a) when the output changes from low to high, this capacitance (C^ has to be charged through the collector resistor R3. This could be a printed circuit board interconnect or quite simply an oscilloscope lead. At the output of all gates there is a capacitive load (CL) caused by the input capacitance of the next stage.
